There is a need for a DPLL circuit with programmable loop parameters and with support for an arbitrary frequency ratio between the reference clock and the VCXO clock that has superior clock timing jitter and wander performance.
Both the foregoing general description and the following detailed description provide examples and are explanatory only. Accordingly, the foregoing general description and the followed detailed description should not be considered to be restrictive. Further, features or variations may be provided in addition to those set forth herein. For example, embodiments may be directed to various feature combinations and sub-combinations described in the detailed description.